The present invention relates to a semiconductor device; and, more particularly, to a method for manufacturing the semiconductor device incorporated therein a contact region with uniformity by using a selective epitaxial growth of a single crystal silicon.
Generally, in a P-N contact semiconductor device, a diffusion region is achieved by annealing after implanting impurity ions into a semiconductor substrate. In order to prevent a short channel effect due to a side diffusion of the diffusion region in a semiconductor device with a narrow channel space, a depth of the diffusion region should be shallow.
Referring to FIGS. 1A to 1F, there are provided cross sectional views setting forth a conventional method for manufacturing a semiconductor device using an enlarged margin self aligned contact (EMSAC).
The manufacturing steps begin with a preparation of a semiconductor substrate 110 incorporating therein isolation regions 112, wherein a reference numeral 160, 180 denote a cell area and a peripheral circuit area, respectively. Thereafter, an gate oxide layer, a gate electrode layer and a mask layer are formed on the semiconductor substrate 110, subsequently, and then they are patterned into a first predetermined configuration, thereby obtaining two gate structures provided with gate dielectrics 114, gate electrodes 116 and mask patterns 118 as shown in FIG. 1A. Here, one gate structure is disposed on the cell area 160 and the other one is disposed on the peripheral area 180.
In a next step as shown in FIG. 1B, impurity ions 145 are implanted into the semiconductor substrate in the cell area 160, thereby obtaining a shallow contact region 122. And then, first side wall spacers 120 are formed on sides of the gate structures.
In an ensuing step, a second insulating layer and a third insulating layer are formed on the semiconductor substrate 110 and the gate structures. And next, the second and the third insulating layers are patterned into a second predetermined configuration using a mask in the cell area 160, whereby a second patterned insulating layer 124A and a third patterned insulating layer 126A are formed in the cell area 160 and a second side wall spacer 124B and a third side wall spacer 126B are formed in the peripheral area 180. Thereafter, the impurity ions are implanted into the semiconductor substrate in the peripheral area 180, thereby obtaining a deep contact region 128 as shown in FIG. 1C.
In a subsequent step, the third patterned insulating layer 126A and the third side wall spacer 126B are removed by a wet etching method using fluoric acid. Then, an interlayer insulating layer 130 is formed on entire surface and flattened by using a chemical mechanical polishing (CMP) technique.
Thereafter, the interlayer insulating layer 130 is selectively etched into a third predetermined configuration using a mask, whereby the interlayer insulating layer 130 in the cell area 160 are removed and the second patterned insulating layer 124A is patterned into a side wall pattern 124Axe2x80x2 as shown in FIG. 1E.
Finally, a conductive layer is deposited on entire surface and flattened by the CMP technique until a height of the conductive layer in the cell area 160 is identical to that of the interlayer insulating layer 130A in the peripheral area 180. Thus, a contact plug 132 is obtained as shown in FIG. 1F.
The conventional method as described above using the EMSAC process has a drawback that total manufacturing steps are too complicated. And further, it takes a long time to adjust uniformity of the surface height delicately when employing the CMP process. Additionally, the shallow contact region to prevent the short channel effect, may be deteriorated due to a loss of the semiconductor substrate.
It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein a shallow contact region in a cell area and a deep contact region in a peripheral area by using a selective epitaxial growth of a single crystal silicon layer, thereby enhancing a contact margin in the cell area and obtaining the deep contact region with a uniform depth in the peripheral region.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing a semiconductor substrate provided with a cell area and a peripheral area; b) forming gate structures formed on the semiconductor substrate which one is disposed in the cell are and the other is disposed in the peripheral area, wherein the gate structures includes gate dielectrics, gate electrodes and mask patterns; c) forming a first side wall spacer on a side of each gate structure; d) growing up a single crystal silicon layer formed on an exposed portion of the semiconductor substrate by using a selective epitaxial growth method; e) forming a second and a third insulating layers on the substrate and the gate structures and patterning into a first predetermined configuration, thereby forming a second and a third patterned insulating layers in the cell area and forming a second and a third side wall spacers in the peripheral area; d) carrying out an ion implantation to semiconductor substrate in the peripheral area; e) removing the third patterned insulating layer and the third side wall spacer; f) forming an interlayer insulating layer on the semiconductor substrate and the gate structures; g) patterning the interlayer insulating layer into a second predetermined configuration, whereby the interlayer insulating layer does not remain in the cell area and the second patterned insulating layer is patterned into a side wall pattern; h) forming a conductive layer on the cell area and the peripheral area; and i) planarizing a surface of the conductive layer, thereby obtaining a contact plug in the cell area.